D_type正反器

module top;
system_clock #100 clock1(data_in);
system_clock #50 clock1(clk);
system_clock #200 clock1(rst);
flip_flop d_type(q,data_in,clk,rst);
endmodule

module flip_flop(q,data_in,clk,rst);
input data_in,clk,rst;
output q;
reg q;
initial
q=0;
always@(posedge clk)
begin
if(rst==1) q=0;
else q=data_in;
end
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)if($time>1000)#(PERIOD-1)$stop;
endmodule

半加法器

module top;
wire a,b;
wire sum,c_out;
system_clock #100 clock1(a);
system_clock #50 clock1(b);
add_half addhalf(sum,c_out,a,b);
endmodule

module add_half(sum,c_out,a,b);
input a,b;
output sum,c_out;
wire c_out_bar;
xor(sum,a,b);
nand(c_out_bar,a,b);
not(c_out,c_out_bar);
endmodule


module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)
if($time>1000)#(PERIOD-1)$stop;
endmodule