module test;
wire q_out;
reg en,data;
initial
begin
data=1;
en=0;
#6 data=0;
#4 en=1;
#2 data=1;
#2 data=0;
#2 data=1;
#4 en=0;
#4 data=0;
#2 data=1;
#2 data=0;
#2 en=1;
#4 data=1;
#4 data=0;
#2 en=0;
#2 data=1;
#8 en=1;
end
latch(q_out,en,data);
endmodule
primitive latch(q_out,en,data);
output q_out;
input en,data;
reg q_out;
table
(10) 0 : ? : 0;
(10) 1 : ? : 1;
(?0) 1 : 1 : 1;
(0?) ? : ? : -;
? (??): ? : -;
endtable
endprimitive
2007年12月21日 星期五
正緣觸發
module test;
wire q_out;
reg en,data;
initial
begin
data=1;
en=0;
#6 data=0;
#4 en=1;
#2 data=1;
#2 data=0;
#2 data=1;
#4 en=0;
#4 data=0;
#2 data=1;
#2 data=0;
#2 en=1;
#4 data=1;
#4 data=0;
#2 en=0;
#2 data=1;
#8 en=1;
end
latch(q_out,en,data);
endmodule
primitive latch(q_out,en,data);
output q_out;
input en,data;
reg q_out;
table
(01) 0 : ? : 0;
(01) 1 : ? : 1;
(0?) 1 : 1 : 1;
(?0) ? : ? : -;
? (??): ? : -;
endtable
endprimitive
wire q_out;
reg en,data;
initial
begin
data=1;
en=0;
#6 data=0;
#4 en=1;
#2 data=1;
#2 data=0;
#2 data=1;
#4 en=0;
#4 data=0;
#2 data=1;
#2 data=0;
#2 en=1;
#4 data=1;
#4 data=0;
#2 en=0;
#2 data=1;
#8 en=1;
end
latch(q_out,en,data);
endmodule
primitive latch(q_out,en,data);
output q_out;
input en,data;
reg q_out;
table
(01) 0 : ? : 0;
(01) 1 : ? : 1;
(0?) 1 : 1 : 1;
(?0) ? : ? : -;
? (??): ? : -;
endtable
endprimitive
負位準觸發
module test;
wire q_out;
reg en,data;
initial
begin
data=1;
en=0;
#6 data=0;
#4 en=1;
#2 data=1;
#2 data=0;
#2 data=1;
#4 en=0;
#4 data=0;
#2 data=1;
#2 data=0;
#2 en=1;
#4 data=1;
#4 data=0;
#2 en=0;
#2 data=1;
#8 en=1;
end
latch(q_out,en,data);
endmodule
primitive latch(q_out,en,data);
output q_out;
input en,data;
reg q_out;
table
0 1 : ? : 1;
0 0 : ? : 0;
1 ? : ? : -;
endtable
endprimitive
wire q_out;
reg en,data;
initial
begin
data=1;
en=0;
#6 data=0;
#4 en=1;
#2 data=1;
#2 data=0;
#2 data=1;
#4 en=0;
#4 data=0;
#2 data=1;
#2 data=0;
#2 en=1;
#4 data=1;
#4 data=0;
#2 en=0;
#2 data=1;
#8 en=1;
end
latch(q_out,en,data);
endmodule
primitive latch(q_out,en,data);
output q_out;
input en,data;
reg q_out;
table
0 1 : ? : 1;
0 0 : ? : 0;
1 ? : ? : -;
endtable
endprimitive
正位準觸發
module test;
wire q_out;
reg en,data;
initial
begin
data=1;
en=0;
#6 data=0;
#4 en=1;
#2 data=1;
#2 data=0;
#2 data=1;
#4 en=0;
#4 data=0;
#2 data=1;
#2 data=0;
#2 en=1;
#4 data=1;
#4 data=0;
#2 en=0;
#2 data=1;
#8 en=1;
end
latch(q_out,en,data);
endmodule
primitive latch(q_out,en,data);
output q_out;
input en,data;
reg q_out;
table
1 1 : ? : 1;
1 0 : ? : 0;
0 ? : ? : -;
endtable
endprimitive
wire q_out;
reg en,data;
initial
begin
data=1;
en=0;
#6 data=0;
#4 en=1;
#2 data=1;
#2 data=0;
#2 data=1;
#4 en=0;
#4 data=0;
#2 data=1;
#2 data=0;
#2 en=1;
#4 data=1;
#4 data=0;
#2 en=0;
#2 data=1;
#8 en=1;
end
latch(q_out,en,data);
endmodule
primitive latch(q_out,en,data);
output q_out;
input en,data;
reg q_out;
table
1 1 : ? : 1;
1 0 : ? : 0;
0 ? : ? : -;
endtable
endprimitive
2007年12月14日 星期五
primitive與module加法器測試
module test;
wire a,b,c_in,sum,sum2,c_out,c_out2;
system_clock #200 clock1(c_in);
system_clock #50 clock2(a);
system_clock #100 clock3(b);
adder xxx2(sum2,a,b,c_in);
adder2 xxx3(c_out2,a,b,c_in);
adder3 xxx1(sum,c_out,a,b,c_in);
always@(c_in or a or b)
begin
if(c_out==c_out2)
if(sum==sum2)
$display ("ture");
else
$display ("sum=%o,sum2=%o",sum,sum2);
else
$display ("c_out=%b,c_out2=%b",c_out,c_out2);
end
endmodule
primitive adder(sum,c_in,a,b);
input c_in,a,b;
output sum;
table
//c_in a b : sum
0 0 0 : 0 ;
0 0 1 : 1 ;
0 1 0 : 1 ;
0 1 1 : 0 ;
1 0 0 : 1 ;
1 0 1 : 0 ;
1 1 0 : 0 ;
1 1 1 : 1 ;
endtable
endprimitive
primitive adder2(c_out,c_in,a,b);
input c_in,a,b;
output c_out;
table
//c_in a b : c_out
0 0 0 : 0;
0 0 1 : 0;
0 1 0 : 0;
0 1 1 : 1;
1 0 0 : 0;
1 0 1 : 1;
1 1 0 : 1;
1 1 1 : 1;
endtable
endprimitive
module adder3(sum,c_out,a,b,c_in);
input a,b;
input c_in;
output sum;
output c_out;
assign {c_out,sum}=a+b+c_in;
endmodule
module system_clock(clk);
parameter period=100;
output clk;
reg clk;
initial clk=0;
always
begin
#(period/2) clk=~clk;
#(period-period/2)clk=~clk;
end
always@(posedge clk)
if($time>1000)#(period-1)$stop;
endmodule
wire a,b,c_in,sum,sum2,c_out,c_out2;
system_clock #200 clock1(c_in);
system_clock #50 clock2(a);
system_clock #100 clock3(b);
adder xxx2(sum2,a,b,c_in);
adder2 xxx3(c_out2,a,b,c_in);
adder3 xxx1(sum,c_out,a,b,c_in);
always@(c_in or a or b)
begin
if(c_out==c_out2)
if(sum==sum2)
$display ("ture");
else
$display ("sum=%o,sum2=%o",sum,sum2);
else
$display ("c_out=%b,c_out2=%b",c_out,c_out2);
end
endmodule
primitive adder(sum,c_in,a,b);
input c_in,a,b;
output sum;
table
//c_in a b : sum
0 0 0 : 0 ;
0 0 1 : 1 ;
0 1 0 : 1 ;
0 1 1 : 0 ;
1 0 0 : 1 ;
1 0 1 : 0 ;
1 1 0 : 0 ;
1 1 1 : 1 ;
endtable
endprimitive
primitive adder2(c_out,c_in,a,b);
input c_in,a,b;
output c_out;
table
//c_in a b : c_out
0 0 0 : 0;
0 0 1 : 0;
0 1 0 : 0;
0 1 1 : 1;
1 0 0 : 0;
1 0 1 : 1;
1 1 0 : 1;
1 1 1 : 1;
endtable
endprimitive
module adder3(sum,c_out,a,b,c_in);
input a,b;
input c_in;
output sum;
output c_out;
assign {c_out,sum}=a+b+c_in;
endmodule
module system_clock(clk);
parameter period=100;
output clk;
reg clk;
initial clk=0;
always
begin
#(period/2) clk=~clk;
#(period-period/2)clk=~clk;
end
always@(posedge clk)
if($time>1000)#(period-1)$stop;
endmodule
2007年12月7日 星期五
危帳練習
module top;
wire f,c_bar,d,e,f0,f1;
reg a,b,c;
initial
begin
#10 a=1; b=1;
#10 c=1;
#10 c=0;
end
initial
#100 $finish;
AND_gate xxx(f0,a,c);
NOT xxx1(c_bar,c);
AND_gate xxx2(f1,b,c_bar);
or_data xx(f,f0,f1);
AND_gate xxx3(f3,a,b);
AND_gate xxx(f4,a,c);
AND_gate xxx2(f5,b,c_bar);
or_data2 xx1(f2,f3,f4,f5);
endmodule
module AND_gate(c,a,b);
input a,b;
output c;
and(c,a,b);
specify
specparam
Tpd_0_1 = 3:3:3,
Tpd_1_0 = 3:3:3;
(a=>c)=(Tpd_0_1,Tpd_1_0);
(b=>c)=(Tpd_0_1,Tpd_1_0);
endspecify
endmodule
module NOT(c_bar,c);
input c;
output c_bar;
wire c;
not(c_bar,c);
specify
specparam
Tpd_0_1 = 3:3:3,
Tpd_1_0 = 3:3:3;
(c=>c_bar)=(Tpd_0_1,Tpd_1_0);
endspecify
endmodule
module or_data(f,f0,f1);
input f0,f1;
output f;
wire f;
or(f,f0,f1);
specify
specparam
Tpd_0_1 = 3:3:3,
Tpd_1_0 = 3:3:3;
(f0=>f)=(Tpd_0_1,Tpd_1_0);
(f1=>f)=(Tpd_0_1,Tpd_1_0);
endspecify
endmodule
module or_data2(f2,f3,f4,f5);
input f3,f4,f5;
output f2;
wire f2;
or(f2,f3,f4,f5);
specify
specparam
Tpd_0_1 = 3:3:3,
Tpd_1_0 = 3:3:3;
(f3=>f2)=(Tpd_0_1,Tpd_1_0);
(f4=>f2)=(Tpd_0_1,Tpd_1_0);
(f5=>f2)=(Tpd_0_1,Tpd_1_0);
endspecify
endmodule
module system_clock(clk);
parameter period=100;
output clk;
reg clk;
initial clk=1;
always
begin
#(period/2) clk=~clk;
#(period-period/2)clk=~clk;
end
always@(posedge clk)
if($time>1000)#(period-1)$stop;
endmodule
wire f,c_bar,d,e,f0,f1;
reg a,b,c;
initial
begin
#10 a=1; b=1;
#10 c=1;
#10 c=0;
end
initial
#100 $finish;
AND_gate xxx(f0,a,c);
NOT xxx1(c_bar,c);
AND_gate xxx2(f1,b,c_bar);
or_data xx(f,f0,f1);
AND_gate xxx3(f3,a,b);
AND_gate xxx(f4,a,c);
AND_gate xxx2(f5,b,c_bar);
or_data2 xx1(f2,f3,f4,f5);
endmodule
module AND_gate(c,a,b);
input a,b;
output c;
and(c,a,b);
specify
specparam
Tpd_0_1 = 3:3:3,
Tpd_1_0 = 3:3:3;
(a=>c)=(Tpd_0_1,Tpd_1_0);
(b=>c)=(Tpd_0_1,Tpd_1_0);
endspecify
endmodule
module NOT(c_bar,c);
input c;
output c_bar;
wire c;
not(c_bar,c);
specify
specparam
Tpd_0_1 = 3:3:3,
Tpd_1_0 = 3:3:3;
(c=>c_bar)=(Tpd_0_1,Tpd_1_0);
endspecify
endmodule
module or_data(f,f0,f1);
input f0,f1;
output f;
wire f;
or(f,f0,f1);
specify
specparam
Tpd_0_1 = 3:3:3,
Tpd_1_0 = 3:3:3;
(f0=>f)=(Tpd_0_1,Tpd_1_0);
(f1=>f)=(Tpd_0_1,Tpd_1_0);
endspecify
endmodule
module or_data2(f2,f3,f4,f5);
input f3,f4,f5;
output f2;
wire f2;
or(f2,f3,f4,f5);
specify
specparam
Tpd_0_1 = 3:3:3,
Tpd_1_0 = 3:3:3;
(f3=>f2)=(Tpd_0_1,Tpd_1_0);
(f4=>f2)=(Tpd_0_1,Tpd_1_0);
(f5=>f2)=(Tpd_0_1,Tpd_1_0);
endspecify
endmodule
module system_clock(clk);
parameter period=100;
output clk;
reg clk;
initial clk=1;
always
begin
#(period/2) clk=~clk;
#(period-period/2)clk=~clk;
end
always@(posedge clk)
if($time>1000)#(period-1)$stop;
endmodule
2007年12月6日 星期四
可改變位元加法器
module top;
wire c_out;
parameter width=8;
reg [width-1:0]a,b;
wire [width-1:0]sum;
integer a1,b1;
initial
begin
for(a1=0;a1<(1<< );a1=a1+1)
begin
for (b1=0;b1<(1<< );b1=b1+1)
begin
{b}=b1;
{a}=a1;
#1;
end
end
$finish;
end
system_clock #200 clock3(c_in);
adder xxx(sum,c_out,a,b,c_in);
endmodule
module adder(sum,c_out,a,b,c_in);
parameter width=8;
input [width-1:0]a,b;
input c_in;
output [width-1:0]sum;
output c_out;
wire [width-1:0]sum;
wire c_out;
assign {c_out,sum}=a+b+c_in;
endmodule
module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)if($time>100000000)#(PERIOD-1)$stop;
endmodule
wire c_out;
parameter width=8;
reg [width-1:0]a,b;
wire [width-1:0]sum;
integer a1,b1;
initial
begin
for(a1=0;a1<(1<< );a1=a1+1)
begin
for (b1=0;b1<(1<< );b1=b1+1)
begin
{b}=b1;
{a}=a1;
#1;
end
end
$finish;
end
system_clock #200 clock3(c_in);
adder xxx(sum,c_out,a,b,c_in);
endmodule
module adder(sum,c_out,a,b,c_in);
parameter width=8;
input [width-1:0]a,b;
input c_in;
output [width-1:0]sum;
output c_out;
wire [width-1:0]sum;
wire c_out;
assign {c_out,sum}=a+b+c_in;
endmodule
module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)if($time>100000000)#(PERIOD-1)$stop;
endmodule
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