primitive與module加法器測試

module test;
wire a,b,c_in,sum,sum2,c_out,c_out2;

system_clock #200 clock1(c_in);
system_clock #50 clock2(a);
system_clock #100 clock3(b);

adder xxx2(sum2,a,b,c_in);
adder2 xxx3(c_out2,a,b,c_in);
adder3 xxx1(sum,c_out,a,b,c_in);

always@(c_in or a or b)
begin
if(c_out==c_out2)
if(sum==sum2)
$display ("ture");
else
$display ("sum=%o,sum2=%o",sum,sum2);
else
$display ("c_out=%b,c_out2=%b",c_out,c_out2);
end
endmodule

primitive adder(sum,c_in,a,b);
input c_in,a,b;
output sum;
table
//c_in a b : sum
0 0 0 : 0 ;
0 0 1 : 1 ;
0 1 0 : 1 ;
0 1 1 : 0 ;
1 0 0 : 1 ;
1 0 1 : 0 ;
1 1 0 : 0 ;
1 1 1 : 1 ;
endtable
endprimitive

primitive adder2(c_out,c_in,a,b);
input c_in,a,b;
output c_out;
table
//c_in a b : c_out
0 0 0 : 0;
0 0 1 : 0;
0 1 0 : 0;
0 1 1 : 1;
1 0 0 : 0;
1 0 1 : 1;
1 1 0 : 1;
1 1 1 : 1;
endtable
endprimitive

module adder3(sum,c_out,a,b,c_in);
input a,b;
input c_in;
output sum;
output c_out;
assign {c_out,sum}=a+b+c_in;
endmodule

module system_clock(clk);
parameter period=100;
output clk;
reg clk;
initial clk=0;
always
begin
#(period/2) clk=~clk;
#(period-period/2)clk=~clk;
end
always@(posedge clk)
if($time>1000)#(period-1)$stop;
endmodule