32位元加法器測試

module test;
wire c_out,c_in,c_out2;
reg [31:0]a,b,a2,b2;
wire [31:0]sum,sum2;
integer a1,b1,a11,b11;
system_clock #200 clock9(c_in);

initial
begin
for(a1=0;a1<65536;a1=a1+1)
begin
for(a11=0;a11<65536;a11=a11+1)
begin
for (b1=0;b1<65536;b1=b1+1)
begin
for (b11=0;b11<65536;b11=b11+1)
begin
{b}=b11;
{a}=a11;
{b2}=b11;
{a2}=a11;
#1;
end
end
end
end
$finish;
end
adder aa(sum,c_out,a,b,c_in);
assign {c_out2,sum2}=a2+b2+c_in;

always@(a2 or b2 or a or b)
begin
if(c_out==c_out2)
if(sum==sum2)
$display ("ture");
else
$display ("sum=%o,sum2=%o,a2=%o,a1=%o,b2=%o,b1=%o",sum,sum2,a2,a,b2,b);
else
$display ("c_out=%b,c_out2=%b,a2=%o,a1=%o,b2=%o,b1=%o",c_out,c_out2,a2,a,b2,b);
end
endmodule

module adder(sum,c_out,a,b,c_in);
input [31:0]a,b;
input c_in;
output [31:0]sum;
output c_out;
assign {c_out,sum}=a+b+c_in;
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)
if($time>100000000)#(PERIOD-1)$stop;
endmodule

3對8解碼器

module top;
wire d7,d6,d5,d4,d3,d2,d1,d0,g,a2,a1,a0;
system_clock #200 clock1(g);
system_clock #100 clock2(a2);
system_clock #50 clock3(a1);
system_clock #25 clock3(a0);

decoder_3to8 xxx(d7,d6,d5,d4,d3,d2,d1,d0,g,a2,a1,a0);
endmodule

module decoder_3to8(d7,d6,d5,d4,d3,d2,d1,d0,g,a2,a1,a0);
input g,a2,a1,a0;
output d7,d6,d5,d4,d3,d2,d1,d0;
reg d7,d6,d5,d4,d3,d2,d1,d0;

always@(g)
begin
if(g==1'b0)
begin
case({a2,a1,a0})
3'b000:
begin
d7=1;d6=1;d5=1;d4=1;d3=1;d2=1;d1=1;d0=0;
end

3'b001:
begin
d7=1;d6=1;d5=1;d4=1;d3=1;d2=1;d1=0;d0=1;
end

3'b010:
begin
d7=1;d6=1;d5=1;d4=1;d3=1;d2=0;d1=1;d0=1;
end

3'b011:
begin
d7=1;d6=1;d5=1;d4=1;d3=0;d2=1;d1=1;d0=1;
end

3'b100:
begin
d7=1;d6=1;d5=1;d4=0;d3=1;d2=1;d1=1;d0=1;
end

3'b101:
begin
d7=1;d6=1;d5=0;d4=1;d3=1;d2=1;d1=1;d0=1;
end

3'b110:
begin
d7=1;d6=0;d5=1;d4=1;d3=1;d2=1;d1=1;d0=1;
end

3'b111:
begin
d7=0;d6=1;d5=1;d4=1;d3=1;d2=1;d1=1;d0=1;
end
endcase
end
else
begin
d7=1;d6=1;d5=1;d4=1;d3=1;d2=1;d1=1;d0=1;
end
end
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)if($time>1000)#(PERIOD-1)$stop;
endmodule

左移運算子練習

module top;
reg [2:0]in;
wire [7:0]out,out2;

initial begin:aa
integer in1;
for(in1=0;in1<8;in1=in1+1)
begin
{in}=in1;
#1;
end
end
decoder xxx(in,out,out2);
always@(out)
begin
$display ("in=%b,in=%o,out=%b,out=%o",in,in,out,out);
end
endmodule

module decoder(in,out,out2);
input [2:0]in;
output [7:0]out,out2;
wire [7:0]out;

//assign out=1'b1<< ;

//assign out2=in<<1;

endmodule

測試4位元加法器

module test;
wire c_in,c_out2;
wire [3:0]a2,b2,sum2;

system_clock #200 clock9(c_in);
system_clock #32 clock1(a2[0]);
system_clock #64 clock2(a2[1]);
system_clock #128 clock3(a2[2]);
system_clock #256 clock4(a2[3]);
system_clock #2 clock5(b2[0]);
system_clock #4 clock6(b2[1]);
system_clock #8 clock7(b2[2]);
system_clock #16 clock8(b2[3]);
adder aa(sum2,c_out2,a2,b2,c_in);

reg [3:0]a,b;
reg [3:0]sum;
reg c_out;
initial begin:yy
integer a1,b1;
for(a1=0;a1<16;a1=a1+1)
begin
for (b1=0;b1<16;b1=b1+1)
begin
{b}=b1;
{a}=a1;
assign {c_out,sum}=a+b+c_in;
#1;
end
end
$finish;
end

always@(a2 or b2 or a or b)
begin
if(c_out==c_out2)
if(sum==sum2)
$display ("ture");
else
$display ("sum=%o,sum2=%o,a2=%o,a1=%o,b2=%o,b1=%o",sum,sum2,a2,a,b2,b);
else
$display ("c_out=%b,c_out2=%b,a2=%o,a1=%o,b2=%o,b1=%o",c_out,c_out2,a2,a,b2,b);
end
endmodule

module adder(sum,c_out,a,b,c_in);
input [3:0]a,b;
input c_in;
output [3:0]sum;
output c_out;
assign {c_out,sum}=a+b+c_in;
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)
if($time>1000)#(PERIOD-1)$stop;
endmodule

4位元加法器~迴圈訊號

module test;
wire c_out,c_in;
system_clock #200 clock9(c_in);
reg [3:0]a,b;
wire [3:0]sum;
initial begin:yy
integer a1,b1;
for(a1=0;a1<16;a1=a1+1)
begin
for (b1=0;b1<16;b1=b1+1)
begin
{b}=b1;
{a}=a1;
#1;
end
end
$finish;
end
adder aa(sum,c_out,a,b,c_in);
endmodule

module adder(sum,c_out,a,b,c_in);
input [3:0]a,b;
input c_in;
output [3:0]sum;
output c_out;
assign {c_out,sum}=a+b+c_in;
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)
if($time>1000)#(PERIOD-1)$stop;
endmodule

期中考~行為模式

真值表~
a0 a1 b0 b1 f
0 0 0 0 0
0 0 0 1 1
0 0 1 0 1
0 0 1 1 0
0 1 0 0 1
0 1 0 1 1
0 1 1 0 0
0 1 1 1 0
1 0 0 0 1
1 0 0 1 0
1 0 1 0 1
1 0 1 1 1
1 1 0 0 0
1 1 0 1 0
1 1 1 0 1
1 1 1 1 1

程式碼~

module top;
system_clock #200 clock1(a0);
system_clock #100 clock2(a1);
system_clock #50 clock3(b0);
system_clock #25 clock4(b1);
many abc(f,a0,a1,b0,b1);
endmodule

module many(f,a0,a1,b0,b1);
input a0,a1,b0,b1;
output f;
assign f=((~a0)&a1&(~b0))|(a0&(~a1)&(~b1))|((~a1)&b0&(~b1))|((~a0)&(~b0)&b1)|(a0&b0);
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)if($time>1000)#(PERIOD-1)$stop;
endmodule

輸入10秒delay的NAND

module top;
reg a,b;
wire i,o;
initial
begin
#10 a=0; b=1;
#10 a=1;
#10 b=0;
#10 b=1;
#10 a=0;
end
initial
#100 $finish;
AND_NOT two(o,i,a,b);
endmodule

module AND_gate(c,a,b);
input a,b;
output c;
and(c,a,b);
specify
specparam
Tpd_0_1 = 3:3:3,
Tpd_1_0 = 3:3:3;
(a=>c)=(Tpd_0_1,Tpd_1_0);
(b=>c)=(Tpd_0_1,Tpd_1_0);
endspecify
endmodule

module AND_NOT(o,i,a,b);
input a,b,i;
output o;
wire c;
AND_gate one(c,a,b);
assign i=c;
not(o,i);
specify
specparam
Tpd_0_1 = 2:2:2,
Tpd_1_0 = 2:2:2;
(i=>o)=(Tpd_0_1,Tpd_1_0);
endspecify
endmodule

NAND延遲共5秒

module top;
wire a,b,o;
system_clock #20 clock1(a);
system_clock #10 clock2(b);
AND_NOT two(o,i,a,b);
endmodule

module AND_gate(c,a,b);
input a,b;
output c;
and(c,a,b);
specify
specparam
Tpd_0_1 = 3:3:3,
Tpd_1_0 = 3:3:3;
(a=>c)=(Tpd_0_1,Tpd_1_0);
(b=>c)=(Tpd_0_1,Tpd_1_0);
endspecify
endmodule

module AND_NOT(o,i,a,b);
input a,b,i;
output o;
wire c;
AND_gate one(c,a,b);
assign i=c;
not(o,i);
specify
specparam
Tpd_0_1 = 2:2:2,
Tpd_1_0 = 2:2:2;
(i=>o)=(Tpd_0_1,Tpd_1_0);
endspecify
endmodule

module system_clock(clk);
parameter period=100;
output clk;
reg clk;
initial clk=0;
always
begin
#(period/2) clk=~clk;
#(period-period/2)clk=~clk;
end
always@(posedge clk)
if($time>1000)#(period-1)$stop;
endmodule

64位元加法器

module top;
wire [63:0]a,b,sum;
system_clock #1 clock1(a[0]);
system_clock #2 clock2(a[1]);
system_clock #4 clock3(a[2]);
system_clock #8 clock4(a[3]);
system_clock #16 clock5(a[4]);
system_clock #32 clock6(a[5]);
system_clock #64 clock7(a[6]);
system_clock #128 clock8(a[7]);
system_clock #256 clock9(a[8]);
system_clock #512 clock10(a[9]);
system_clock #1024 clock11(a[10]);
system_clock #2048 clock12(a[11]);
system_clock #4096 clock13(a[12]);
system_clock #8192 clock14(a[13]);
system_clock #16384 clock15(a[14]);
system_clock #32768 clock16(a[15]);
system_clock #65536 clock17(a[16]);
system_clock #131072 clock18(a[17]);
system_clock #262144 clock19(a[18]);
system_clock #524288 clock20(a[19]);
system_clock #1048576 clock21(a[20]);
system_clock #2097152 clock22(a[21]);
system_clock #4194304 clock23(a[22]);
system_clock #8388608 clock24(a[23]);
system_clock #16777216 clock25(a[24]);
system_clock #33554432 clock26(a[25]);
system_clock #67108864 clock27(a[26]);
system_clock #134217728 clock28(a[27]);
system_clock #268435456 clock29(a[28]);
system_clock #536870912 clock30(a[29]);
system_clock #1073741824 clock31(a[30]);
system_clock #2147483648 clock32(a[31]);
system_clock #4294967296 clock33(a[32]);
system_clock #8589934592 clock34(a[33]);
system_clock #17179869184 clock35(a[34]);
system_clock #34359738368 clock36(a[35]);
system_clock #68719476736 clock37(a[36]);
system_clock #137438953472 clock38(a[37]);
system_clock #274877906944 clock39(a[38]);
system_clock #549755813888 clock40(a[39]);
system_clock #1099511627776 clock41(a[40]);
system_clock #2199023255552 clock42(a[41]);
system_clock #4398046511104 clock43(a[42]);
system_clock #8796093022208 clock44(a[43]);
system_clock #17592186044416 clock45(a[44]);
system_clock #35184372088832 clock46(a[45]);
system_clock #70368744177664 clock47(a[46]);
system_clock #140737488355328 clock48(a[47]);
system_clock #281474976710656 clock49(a[48]);
system_clock #562949953421312 clock50(a[49]);
system_clock #1125899906842624 clock51(a[50]);
system_clock #2251799813685248 clock52(a[51]);
system_clock #4503599627370496 clock53(a[52]);
system_clock #9007199254740992 clock54(a[53]);
system_clock #18014398509481984 clock55(a[54]);
system_clock #36028797018963968 clock56(a[55]);
system_clock #72057594037927936 clock57(a[56]);
system_clock #144115188075855872 clock58(a[57]);
system_clock #288230376151711744 clock59(a[58]);
system_clock #576460752303423488 clock60(a[59]);
system_clock #1152921504606846976 clock61(a[60]);
system_clock #2305843009213693952 clock62(a[61]);
system_clock #4611686018427387904 clock63(a[62]);
system_clock #9223372036854775808 clock64(a[63]);

system_clock #1 clock1(b[0]);
system_clock #2 clock2(b[1]);
system_clock #4 clock3(b[2]);
system_clock #8 clock4(b[3]);
system_clock #16 clock5(b[4]);
system_clock #32 clock6(b[5]);
system_clock #64 clock7(b[6]);
system_clock #128 clock8(b[7]);
system_clock #256 clock9(b[8]);
system_clock #512 clock10(b[9]);
system_clock #1024 clock11(b[10]);
system_clock #2048 clock12(b[11]);
system_clock #4096 clock13(b[12]);
system_clock #8192 clock14(b[13]);
system_clock #16384 clock15(b[14]);
system_clock #32768 clock16(b[15]);
system_clock #65536 clock17(b[16]);
system_clock #131072 clock18(b[17]);
system_clock #262144 clock19(b[18]);
system_clock #524288 clock20(b[19]);
system_clock #1048576 clock21(b[20]);
system_clock #2097152 clock22(b[21]);
system_clock #4194304 clock23(b[22]);
system_clock #8388608 clock24(b[23]);
system_clock #16777216 clock25(b[24]);
system_clock #33554432 clock26(b[25]);
system_clock #67108864 clock27(b[26]);
system_clock #134217728 clock28(b[27]);
system_clock #268435456 clock29(b[28]);
system_clock #536870912 clock30(b[29]);
system_clock #1073741824 clock31(b[30]);
system_clock #2147483648 clock32(b[31]);
system_clock #4294967296 clock33(b[32]);
system_clock #8589934592 clock34(b[33]);
system_clock #17179869184 clock35(b[34]);
system_clock #34359738368 clock36(b[35]);
system_clock #68719476736 clock37(b[36]);
system_clock #137438953472 clock38(b[37]);
system_clock #274877906944 clock39(b[38]);
system_clock #549755813888 clock40(b[39]);
system_clock #1099511627776 clock41(b[40]);
system_clock #2199023255552 clock42(b[41]);
system_clock #4398046511104 clock43(b[42]);
system_clock #8796093022208 clock44(b[43]);
system_clock #17592186044416 clock45(b[44]);
system_clock #35184372088832 clock46(b[45]);
system_clock #70368744177664 clock47(b[46]);
system_clock #140737488355328 clock48(b[47]);
system_clock #281474976710656 clock49(b[48]);
system_clock #562949953421312 clock50(b[49]);
system_clock #1125899906842624 clock51(b[50]);
system_clock #2251799813685248 clock52(b[51]);
system_clock #4503599627370496 clock53(b[52]);
system_clock #9007199254740992 clock54(b[53]);
system_clock #18014398509481984 clock55(b[54]);
system_clock #36028797018963968 clock56(b[55]);
system_clock #72057594037927936 clock57(b[56]);
system_clock #144115188075855872 clock58(b[57]);
system_clock #288230376151711744 clock59(b[58]);
system_clock #576460752303423488 clock60(b[59]);
system_clock #1152921504606846976 clock61(b[60]);
system_clock #2305843009213693952 clock62(b[61]);
system_clock #4611686018427387904 clock63(b[62]);
system_clock #9223372036854775808 clock64(b[63]);

system_clock #200 clock33(c_in);
adder_64bits x5(sum,c_out,a,b,c_in);
endmodule

module add_half(sum,c_out,a,b);
input a,b;
output sum,c_out;
xor(sum,a,b);
and(c_out,a,b);
endmodule

module add_full(sum2,c_out2,c_in,a,b);
input a,b,c_in;
output sum2,c_out2;
wire w1,w2,w3;
add_half ONE(w1,w2,a,b);
add_half TWO(sum2,w3,c_in,w1);
or(c_out2,w3,w2);
endmodule

module adder_4bits(sum,c_out,a,b,c_in);
input [3:0]a,b;
input c_in;
output [3:0]sum;
output c_out;
wire w1,w2,w3;
add_full x1(sum[0],w1,a[0],b[0],c_in);
add_full x2(sum[1],w2,a[1],b[1],w1);
add_full x3(sum[2],w3,a[2],b[2],w2);
add_full x4(sum[3],c_out,a[3],b[3],w3);
endmodule

module adder_16bits(sum,c_out,a,b,c_in);
input [15:0]a,b;
input c_in;
output [15:0]sum;
output c_out;
wire w1,w2,w3;
adder_4bits x1(sum[3:0],w1,a[3:0],b[3:0],c_in);
adder_4bits x2(sum[7:4],w2,a[7:4],b[7:4],w1);
adder_4bits x3(sum[11:8],w3,a[11:8],b[11:8],w2);
adder_4bits x4(sum[15:12],c_out,a[15:12],b[15:12],w3);
endmodule

module adder_64bits(sum,c_out,a,b,c_in);
input [63:0]a,b;
input c_in;
output [63:0]sum;
output c_out;
wire w1,w2,w3;
adder_16bits x1(sum[15:0],w1,a[15:0],b[15:0],c_in);
adder_16bits x2(sum[31:16],w2,a[31:16],b[31:16],w1);
adder_16bits x3(sum[47:17],w3,a[47:17],b[47:17],w2);
adder_16bits x4(sum[63:18],c_out,a[63:18],b[63:18],w3);
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)
if($time>1000)#(PERIOD-1)$stop;
endmodule

16位元加法器

module top;
wire [15:0]a,b,sum;
system_clock #1 clock1(a[0]);
system_clock #2 clock2(a[1]);
system_clock #4 clock3(a[2]);
system_clock #8 clock4(a[3]);
system_clock #16 clock5(a[4]);
system_clock #32 clock6(a[5]);
system_clock #64 clock7(a[6]);
system_clock #128 clock8(a[7]);
system_clock #256 clock9(a[8]);
system_clock #512 clock10(a[9]);
system_clock #1024 clock11(a[10]);
system_clock #2048 clock12(a[11]);
system_clock #4096 clock13(a[12]);
system_clock #8192 clock14(a[13]);
system_clock #16384 clock15(a[14]);
system_clock #32768 clock16(a[15]);

system_clock #1 clock17(b[0]);
system_clock #2 clock18(b[1]);
system_clock #4 clock19(b[2]);
system_clock #8 clock20(b[3]);
system_clock #16 clock21(b[4]);
system_clock #32 clock22(b[5]);
system_clock #64 clock23(b[6]);
system_clock #128 clock24(b[7]);
system_clock #256 clock25(b[8]);
system_clock #512 clock26(b[9]);
system_clock #1024 clock27(b[10]);
system_clock #2048 clock28(b[11]);
system_clock #4096 clock29(b[12]);
system_clock #8192 clock30(b[13]);
system_clock #16384 clock31(b[14]);
system_clock #32768 clock32(b[15]);
system_clock #200 clock33(c_in);
adder_16bits x5(sum,c_out,a,b,c_in);
endmodule

module add_half(sum,c_out,a,b);
input a,b;
output sum,c_out;
xor(sum,a,b);
and(c_out,a,b);
endmodule

module add_full(sum2,c_out2,c_in,a,b);
input a,b,c_in;
output sum2,c_out2;
wire w1,w2,w3;
add_half ONE(w1,w2,a,b);
add_half TWO(sum2,w3,c_in,w1);
or(c_out2,w3,w2);
endmodule

module adder_4bits(sum,c_out,a,b,c_in);
input [3:0]a,b;
input c_in;
output [3:0]sum;
output c_out;
wire w1,w2,w3;
add_full x1(sum[0],w1,a[0],b[0],c_in);
add_full x2(sum[1],w2,a[1],b[1],w1);
add_full x3(sum[2],w3,a[2],b[2],w2);
add_full x4(sum[3],c_out,a[3],b[3],w3);
endmodule

module adder_16bits(sum,c_out,a,b,c_in);
input [15:0]a,b;
input c_in;
output [15:0]sum;
output c_out;
wire w1,w2,w3;
adder_4bits x1(sum[3:0],w1,a[3:0],b[3:0],c_in);
adder_4bits x2(sum[7:4],w2,a[7:4],b[7:4],w1);
adder_4bits x3(sum[11:8],w3,a[11:8],b[11:8],w2);
adder_4bits x4(sum[15:12],c_out,a[15:12],b[15:12],w3);
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)
if($time>1000)#(PERIOD-1)$stop;
endmodule

4位元加法器

module top;
wire [3:0]a,b,sum;
system_clock #10 clock1(a[0]);
system_clock #20 clock2(a[1]);
system_clock #40 clock3(a[2]);
system_clock #80 clock4(a[3]);
system_clock #10 clock5(b[0]);
system_clock #20 clock6(b[1]);
system_clock #40 clock7(b[2]);
system_clock #80 clock8(b[3]);
system_clock #200 clock9(c_in);
adder_4bits x5(sum,c_out,a,b,c_in);
endmodule

module add_half(sum,c_out,a,b);
input a,b;
output sum,c_out;
xor(sum,a,b);
and(c_out,a,b);
endmodule

module add_full(sum2,c_out2,c_in,a,b);
input a,b,c_in;
output sum2,c_out2;
wire w1,w2,w3;
add_half ONE(w1,w2,a,b);
add_half TWO(sum2,w3,c_in,w1);
or(c_out2,w3,w2);
endmodule

module adder_4bits(sum,c_out,a,b,c_in);
input [3:0]a,b;
input c_in;
output [3:0]sum;
output c_out;
wire w1,w2,w3;
add_full x1(sum[0],w1,a[0],b[0],c_in);
add_full x2(sum[1],w2,a[1],b[1],w1);
add_full x3(sum[2],w3,a[2],b[2],w2);
add_full x4(sum[3],c_out,a[3],b[3],w3);
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)
if($time>1000)#(PERIOD-1)$stop;
endmodule

期中考考試

真值表~
a0 a1 b0 b1 f
0 0 0 0 0
0 0 0 1 1
0 0 1 0 1
0 0 1 1 0
0 1 0 0 1
0 1 0 1 1
0 1 1 0 0
0 1 1 1 0
1 0 0 0 1
1 0 0 1 0
1 0 1 0 1
1 0 1 1 1
1 1 0 0 0
1 1 0 1 0
1 1 1 0 1
1 1 1 1 1

程式碼~
module top;
system_clock #200 clock1(a0);
system_clock #100 clock2(a1);
system_clock #50 clock3(b0);
system_clock #25 clock4(b1);
many abc(f,a0,a1,b0,b1);
endmodule

module many(f,a0,a1,b0,b1);
input a0,a1,b0,b1;
output f;
wire a0_1,a1_1,b0_1,b1_1,c,d,e,g,h;
not(a0_1,a0);
not(a1_1,a1);
not(b0_1,b0);
not(b1_1,b1);
and(c,a0_1,a1,b0_1);
and(d,a0,a1_1,b1_1);
and(e,a1_1,b0,b1_1);
and(g,a0_1,b0_1,b1);
and(h,a0,b0);
or(f,c,d,e,g,h);
endmodule


module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)if($time>1000)#(PERIOD-1)$stop;
endmodule

反向器delay程式

module top;
wire o,a;
system_clock #20 clock1(a);
delay abc(o,a);
endmodule

module delay(o,a);
input a;
output o;
not(o,a);

specify
specparam
Tpd_0_1 = 2:2:2,
Tpd_1_0 = 2:2:2;
(a=>o)=(Tpd_0_1,Tpd_1_0);
endspecify
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=1;
always
begin
#(PERIOD/10)clk=~clk;
#(PERIOD-PERIOD/10)clk=~clk;
end
always@(posedge clk)if($time>1000)#(PERIOD-1)$stop;
endmodule

期中考~多腳位輸入

輸入訊號:
input output

a b c d f

0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 1
0 1 1 1 1
1 0 0 0 1
1 0 0 1 1
1 0 1 0 0
1 0 1 1 0
1 1 0 0 1
1 1 0 1 1
1 1 1 0 0
1 1 1 1 0

程式碼:
module top;
system_clock #200 clock1(a);
system_clock #100 clock2(b);
system_clock #50 clock3(c);
system_clock #25 clock3(d);
many abc(f,a,b,c);
endmodule

module many(f,a,b,c,d);
input a,b,c,d;
output f;
wire a_0,c_0,f_1,f_2;
not(c_0,c);
not(a_0,a);
and(f_1,a,c_0);
and(f_2,a_0,b,c);
or(f,f_1,f_2);
endmodule


module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)if($time>1000)#(PERIOD-1)$stop;
endmodule

1位元全加法器

module top;
system_clock #100 clock1(a);
system_clock #50 clock2(b);
system_clock #200 clock3(c_in);
fulladder ab(sum,c_out,a,b,c_in);
endmodule

module add_half(sum,c_out,a,b);
input a,b;
output sum,c_out;
wire c_out_bar;
xor(sum,a,b);
and(c_out,a,b);
endmodule


module fulladder(sum,c_out,a,b,c_in);
input a,b,c_in;
output sum,c_out;
wire w1,w2,w3;
add_half abc(w1,w2,a,b);
add_half abcd(sum,w3,w1,c_in);
or(c_out,w2,w3);
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)
if($time>1000)#(PERIOD-1)$stop;
endmodule