反向器delay程式

module top;
wire o,a;
system_clock #20 clock1(a);
delay abc(o,a);
endmodule

module delay(o,a);
input a;
output o;
not(o,a);

specify
specparam
Tpd_0_1 = 2:2:2,
Tpd_1_0 = 2:2:2;
(a=>o)=(Tpd_0_1,Tpd_1_0);
endspecify
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=1;
always
begin
#(PERIOD/10)clk=~clk;
#(PERIOD-PERIOD/10)clk=~clk;
end
always@(posedge clk)if($time>1000)#(PERIOD-1)$stop;
endmodule