4位元加法器~迴圈訊號

module test;
wire c_out,c_in;
system_clock #200 clock9(c_in);
reg [3:0]a,b;
wire [3:0]sum;
initial begin:yy
integer a1,b1;
for(a1=0;a1<16;a1=a1+1)
begin
for (b1=0;b1<16;b1=b1+1)
begin
{b}=b1;
{a}=a1;
#1;
end
end
$finish;
end
adder aa(sum,c_out,a,b,c_in);
endmodule

module adder(sum,c_out,a,b,c_in);
input [3:0]a,b;
input c_in;
output [3:0]sum;
output c_out;
assign {c_out,sum}=a+b+c_in;
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)
if($time>1000)#(PERIOD-1)$stop;
endmodule