測試4位元加法器

module test;
wire c_in,c_out2;
wire [3:0]a2,b2,sum2;

system_clock #200 clock9(c_in);
system_clock #32 clock1(a2[0]);
system_clock #64 clock2(a2[1]);
system_clock #128 clock3(a2[2]);
system_clock #256 clock4(a2[3]);
system_clock #2 clock5(b2[0]);
system_clock #4 clock6(b2[1]);
system_clock #8 clock7(b2[2]);
system_clock #16 clock8(b2[3]);
adder aa(sum2,c_out2,a2,b2,c_in);

reg [3:0]a,b;
reg [3:0]sum;
reg c_out;
initial begin:yy
integer a1,b1;
for(a1=0;a1<16;a1=a1+1)
begin
for (b1=0;b1<16;b1=b1+1)
begin
{b}=b1;
{a}=a1;
assign {c_out,sum}=a+b+c_in;
#1;
end
end
$finish;
end

always@(a2 or b2 or a or b)
begin
if(c_out==c_out2)
if(sum==sum2)
$display ("ture");
else
$display ("sum=%o,sum2=%o,a2=%o,a1=%o,b2=%o,b1=%o",sum,sum2,a2,a,b2,b);
else
$display ("c_out=%b,c_out2=%b,a2=%o,a1=%o,b2=%o,b1=%o",c_out,c_out2,a2,a,b2,b);
end
endmodule

module adder(sum,c_out,a,b,c_in);
input [3:0]a,b;
input c_in;
output [3:0]sum;
output c_out;
assign {c_out,sum}=a+b+c_in;
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)
if($time>1000)#(PERIOD-1)$stop;
endmodule