32位元加法器測試

module test;
wire c_out,c_in,c_out2;
reg [31:0]a,b,a2,b2;
wire [31:0]sum,sum2;
integer a1,b1,a11,b11;
system_clock #200 clock9(c_in);

initial
begin
for(a1=0;a1<65536;a1=a1+1)
begin
for(a11=0;a11<65536;a11=a11+1)
begin
for (b1=0;b1<65536;b1=b1+1)
begin
for (b11=0;b11<65536;b11=b11+1)
begin
{b}=b11;
{a}=a11;
{b2}=b11;
{a2}=a11;
#1;
end
end
end
end
$finish;
end
adder aa(sum,c_out,a,b,c_in);
assign {c_out2,sum2}=a2+b2+c_in;

always@(a2 or b2 or a or b)
begin
if(c_out==c_out2)
if(sum==sum2)
$display ("ture");
else
$display ("sum=%o,sum2=%o,a2=%o,a1=%o,b2=%o,b1=%o",sum,sum2,a2,a,b2,b);
else
$display ("c_out=%b,c_out2=%b,a2=%o,a1=%o,b2=%o,b1=%o",c_out,c_out2,a2,a,b2,b);
end
endmodule

module adder(sum,c_out,a,b,c_in);
input [31:0]a,b;
input c_in;
output [31:0]sum;
output c_out;
assign {c_out,sum}=a+b+c_in;
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)
if($time>100000000)#(PERIOD-1)$stop;
endmodule