左移運算子練習

module top;
reg [2:0]in;
wire [7:0]out,out2;

initial begin:aa
integer in1;
for(in1=0;in1<8;in1=in1+1)
begin
{in}=in1;
#1;
end
end
decoder xxx(in,out,out2);
always@(out)
begin
$display ("in=%b,in=%o,out=%b,out=%o",in,in,out,out);
end
endmodule

module decoder(in,out,out2);
input [2:0]in;
output [7:0]out,out2;
wire [7:0]out;

//assign out=1'b1<< ;

//assign out2=in<<1;

endmodule