4位元加法器

module top;
wire [3:0]a,b,sum;
system_clock #10 clock1(a[0]);
system_clock #20 clock2(a[1]);
system_clock #40 clock3(a[2]);
system_clock #80 clock4(a[3]);
system_clock #10 clock5(b[0]);
system_clock #20 clock6(b[1]);
system_clock #40 clock7(b[2]);
system_clock #80 clock8(b[3]);
system_clock #200 clock9(c_in);
adder_4bits x5(sum,c_out,a,b,c_in);
endmodule

module add_half(sum,c_out,a,b);
input a,b;
output sum,c_out;
xor(sum,a,b);
and(c_out,a,b);
endmodule

module add_full(sum2,c_out2,c_in,a,b);
input a,b,c_in;
output sum2,c_out2;
wire w1,w2,w3;
add_half ONE(w1,w2,a,b);
add_half TWO(sum2,w3,c_in,w1);
or(c_out2,w3,w2);
endmodule

module adder_4bits(sum,c_out,a,b,c_in);
input [3:0]a,b;
input c_in;
output [3:0]sum;
output c_out;
wire w1,w2,w3;
add_full x1(sum[0],w1,a[0],b[0],c_in);
add_full x2(sum[1],w2,a[1],b[1],w1);
add_full x3(sum[2],w3,a[2],b[2],w2);
add_full x4(sum[3],c_out,a[3],b[3],w3);
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)
if($time>1000)#(PERIOD-1)$stop;
endmodule