16位元加法器

module top;
wire [15:0]a,b,sum;
system_clock #1 clock1(a[0]);
system_clock #2 clock2(a[1]);
system_clock #4 clock3(a[2]);
system_clock #8 clock4(a[3]);
system_clock #16 clock5(a[4]);
system_clock #32 clock6(a[5]);
system_clock #64 clock7(a[6]);
system_clock #128 clock8(a[7]);
system_clock #256 clock9(a[8]);
system_clock #512 clock10(a[9]);
system_clock #1024 clock11(a[10]);
system_clock #2048 clock12(a[11]);
system_clock #4096 clock13(a[12]);
system_clock #8192 clock14(a[13]);
system_clock #16384 clock15(a[14]);
system_clock #32768 clock16(a[15]);

system_clock #1 clock17(b[0]);
system_clock #2 clock18(b[1]);
system_clock #4 clock19(b[2]);
system_clock #8 clock20(b[3]);
system_clock #16 clock21(b[4]);
system_clock #32 clock22(b[5]);
system_clock #64 clock23(b[6]);
system_clock #128 clock24(b[7]);
system_clock #256 clock25(b[8]);
system_clock #512 clock26(b[9]);
system_clock #1024 clock27(b[10]);
system_clock #2048 clock28(b[11]);
system_clock #4096 clock29(b[12]);
system_clock #8192 clock30(b[13]);
system_clock #16384 clock31(b[14]);
system_clock #32768 clock32(b[15]);
system_clock #200 clock33(c_in);
adder_16bits x5(sum,c_out,a,b,c_in);
endmodule

module add_half(sum,c_out,a,b);
input a,b;
output sum,c_out;
xor(sum,a,b);
and(c_out,a,b);
endmodule

module add_full(sum2,c_out2,c_in,a,b);
input a,b,c_in;
output sum2,c_out2;
wire w1,w2,w3;
add_half ONE(w1,w2,a,b);
add_half TWO(sum2,w3,c_in,w1);
or(c_out2,w3,w2);
endmodule

module adder_4bits(sum,c_out,a,b,c_in);
input [3:0]a,b;
input c_in;
output [3:0]sum;
output c_out;
wire w1,w2,w3;
add_full x1(sum[0],w1,a[0],b[0],c_in);
add_full x2(sum[1],w2,a[1],b[1],w1);
add_full x3(sum[2],w3,a[2],b[2],w2);
add_full x4(sum[3],c_out,a[3],b[3],w3);
endmodule

module adder_16bits(sum,c_out,a,b,c_in);
input [15:0]a,b;
input c_in;
output [15:0]sum;
output c_out;
wire w1,w2,w3;
adder_4bits x1(sum[3:0],w1,a[3:0],b[3:0],c_in);
adder_4bits x2(sum[7:4],w2,a[7:4],b[7:4],w1);
adder_4bits x3(sum[11:8],w3,a[11:8],b[11:8],w2);
adder_4bits x4(sum[15:12],c_out,a[15:12],b[15:12],w3);
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)
if($time>1000)#(PERIOD-1)$stop;
endmodule