64位元加法器

module top;
wire [63:0]a,b,sum;
system_clock #1 clock1(a[0]);
system_clock #2 clock2(a[1]);
system_clock #4 clock3(a[2]);
system_clock #8 clock4(a[3]);
system_clock #16 clock5(a[4]);
system_clock #32 clock6(a[5]);
system_clock #64 clock7(a[6]);
system_clock #128 clock8(a[7]);
system_clock #256 clock9(a[8]);
system_clock #512 clock10(a[9]);
system_clock #1024 clock11(a[10]);
system_clock #2048 clock12(a[11]);
system_clock #4096 clock13(a[12]);
system_clock #8192 clock14(a[13]);
system_clock #16384 clock15(a[14]);
system_clock #32768 clock16(a[15]);
system_clock #65536 clock17(a[16]);
system_clock #131072 clock18(a[17]);
system_clock #262144 clock19(a[18]);
system_clock #524288 clock20(a[19]);
system_clock #1048576 clock21(a[20]);
system_clock #2097152 clock22(a[21]);
system_clock #4194304 clock23(a[22]);
system_clock #8388608 clock24(a[23]);
system_clock #16777216 clock25(a[24]);
system_clock #33554432 clock26(a[25]);
system_clock #67108864 clock27(a[26]);
system_clock #134217728 clock28(a[27]);
system_clock #268435456 clock29(a[28]);
system_clock #536870912 clock30(a[29]);
system_clock #1073741824 clock31(a[30]);
system_clock #2147483648 clock32(a[31]);
system_clock #4294967296 clock33(a[32]);
system_clock #8589934592 clock34(a[33]);
system_clock #17179869184 clock35(a[34]);
system_clock #34359738368 clock36(a[35]);
system_clock #68719476736 clock37(a[36]);
system_clock #137438953472 clock38(a[37]);
system_clock #274877906944 clock39(a[38]);
system_clock #549755813888 clock40(a[39]);
system_clock #1099511627776 clock41(a[40]);
system_clock #2199023255552 clock42(a[41]);
system_clock #4398046511104 clock43(a[42]);
system_clock #8796093022208 clock44(a[43]);
system_clock #17592186044416 clock45(a[44]);
system_clock #35184372088832 clock46(a[45]);
system_clock #70368744177664 clock47(a[46]);
system_clock #140737488355328 clock48(a[47]);
system_clock #281474976710656 clock49(a[48]);
system_clock #562949953421312 clock50(a[49]);
system_clock #1125899906842624 clock51(a[50]);
system_clock #2251799813685248 clock52(a[51]);
system_clock #4503599627370496 clock53(a[52]);
system_clock #9007199254740992 clock54(a[53]);
system_clock #18014398509481984 clock55(a[54]);
system_clock #36028797018963968 clock56(a[55]);
system_clock #72057594037927936 clock57(a[56]);
system_clock #144115188075855872 clock58(a[57]);
system_clock #288230376151711744 clock59(a[58]);
system_clock #576460752303423488 clock60(a[59]);
system_clock #1152921504606846976 clock61(a[60]);
system_clock #2305843009213693952 clock62(a[61]);
system_clock #4611686018427387904 clock63(a[62]);
system_clock #9223372036854775808 clock64(a[63]);

system_clock #1 clock1(b[0]);
system_clock #2 clock2(b[1]);
system_clock #4 clock3(b[2]);
system_clock #8 clock4(b[3]);
system_clock #16 clock5(b[4]);
system_clock #32 clock6(b[5]);
system_clock #64 clock7(b[6]);
system_clock #128 clock8(b[7]);
system_clock #256 clock9(b[8]);
system_clock #512 clock10(b[9]);
system_clock #1024 clock11(b[10]);
system_clock #2048 clock12(b[11]);
system_clock #4096 clock13(b[12]);
system_clock #8192 clock14(b[13]);
system_clock #16384 clock15(b[14]);
system_clock #32768 clock16(b[15]);
system_clock #65536 clock17(b[16]);
system_clock #131072 clock18(b[17]);
system_clock #262144 clock19(b[18]);
system_clock #524288 clock20(b[19]);
system_clock #1048576 clock21(b[20]);
system_clock #2097152 clock22(b[21]);
system_clock #4194304 clock23(b[22]);
system_clock #8388608 clock24(b[23]);
system_clock #16777216 clock25(b[24]);
system_clock #33554432 clock26(b[25]);
system_clock #67108864 clock27(b[26]);
system_clock #134217728 clock28(b[27]);
system_clock #268435456 clock29(b[28]);
system_clock #536870912 clock30(b[29]);
system_clock #1073741824 clock31(b[30]);
system_clock #2147483648 clock32(b[31]);
system_clock #4294967296 clock33(b[32]);
system_clock #8589934592 clock34(b[33]);
system_clock #17179869184 clock35(b[34]);
system_clock #34359738368 clock36(b[35]);
system_clock #68719476736 clock37(b[36]);
system_clock #137438953472 clock38(b[37]);
system_clock #274877906944 clock39(b[38]);
system_clock #549755813888 clock40(b[39]);
system_clock #1099511627776 clock41(b[40]);
system_clock #2199023255552 clock42(b[41]);
system_clock #4398046511104 clock43(b[42]);
system_clock #8796093022208 clock44(b[43]);
system_clock #17592186044416 clock45(b[44]);
system_clock #35184372088832 clock46(b[45]);
system_clock #70368744177664 clock47(b[46]);
system_clock #140737488355328 clock48(b[47]);
system_clock #281474976710656 clock49(b[48]);
system_clock #562949953421312 clock50(b[49]);
system_clock #1125899906842624 clock51(b[50]);
system_clock #2251799813685248 clock52(b[51]);
system_clock #4503599627370496 clock53(b[52]);
system_clock #9007199254740992 clock54(b[53]);
system_clock #18014398509481984 clock55(b[54]);
system_clock #36028797018963968 clock56(b[55]);
system_clock #72057594037927936 clock57(b[56]);
system_clock #144115188075855872 clock58(b[57]);
system_clock #288230376151711744 clock59(b[58]);
system_clock #576460752303423488 clock60(b[59]);
system_clock #1152921504606846976 clock61(b[60]);
system_clock #2305843009213693952 clock62(b[61]);
system_clock #4611686018427387904 clock63(b[62]);
system_clock #9223372036854775808 clock64(b[63]);

system_clock #200 clock33(c_in);
adder_64bits x5(sum,c_out,a,b,c_in);
endmodule

module add_half(sum,c_out,a,b);
input a,b;
output sum,c_out;
xor(sum,a,b);
and(c_out,a,b);
endmodule

module add_full(sum2,c_out2,c_in,a,b);
input a,b,c_in;
output sum2,c_out2;
wire w1,w2,w3;
add_half ONE(w1,w2,a,b);
add_half TWO(sum2,w3,c_in,w1);
or(c_out2,w3,w2);
endmodule

module adder_4bits(sum,c_out,a,b,c_in);
input [3:0]a,b;
input c_in;
output [3:0]sum;
output c_out;
wire w1,w2,w3;
add_full x1(sum[0],w1,a[0],b[0],c_in);
add_full x2(sum[1],w2,a[1],b[1],w1);
add_full x3(sum[2],w3,a[2],b[2],w2);
add_full x4(sum[3],c_out,a[3],b[3],w3);
endmodule

module adder_16bits(sum,c_out,a,b,c_in);
input [15:0]a,b;
input c_in;
output [15:0]sum;
output c_out;
wire w1,w2,w3;
adder_4bits x1(sum[3:0],w1,a[3:0],b[3:0],c_in);
adder_4bits x2(sum[7:4],w2,a[7:4],b[7:4],w1);
adder_4bits x3(sum[11:8],w3,a[11:8],b[11:8],w2);
adder_4bits x4(sum[15:12],c_out,a[15:12],b[15:12],w3);
endmodule

module adder_64bits(sum,c_out,a,b,c_in);
input [63:0]a,b;
input c_in;
output [63:0]sum;
output c_out;
wire w1,w2,w3;
adder_16bits x1(sum[15:0],w1,a[15:0],b[15:0],c_in);
adder_16bits x2(sum[31:16],w2,a[31:16],b[31:16],w1);
adder_16bits x3(sum[47:17],w3,a[47:17],b[47:17],w2);
adder_16bits x4(sum[63:18],c_out,a[63:18],b[63:18],w3);
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)
if($time>1000)#(PERIOD-1)$stop;
endmodule