1位元全加法器

module top;
system_clock #100 clock1(a);
system_clock #50 clock2(b);
system_clock #200 clock3(c_in);
fulladder ab(sum,c_out,a,b,c_in);
endmodule

module add_half(sum,c_out,a,b);
input a,b;
output sum,c_out;
wire c_out_bar;
xor(sum,a,b);
and(c_out,a,b);
endmodule


module fulladder(sum,c_out,a,b,c_in);
input a,b,c_in;
output sum,c_out;
wire w1,w2,w3;
add_half abc(w1,w2,a,b);
add_half abcd(sum,w3,w1,c_in);
or(c_out,w2,w3);
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)
if($time>1000)#(PERIOD-1)$stop;
endmodule