NAND延遲共5秒

module top;
wire a,b,o;
system_clock #20 clock1(a);
system_clock #10 clock2(b);
AND_NOT two(o,i,a,b);
endmodule

module AND_gate(c,a,b);
input a,b;
output c;
and(c,a,b);
specify
specparam
Tpd_0_1 = 3:3:3,
Tpd_1_0 = 3:3:3;
(a=>c)=(Tpd_0_1,Tpd_1_0);
(b=>c)=(Tpd_0_1,Tpd_1_0);
endspecify
endmodule

module AND_NOT(o,i,a,b);
input a,b,i;
output o;
wire c;
AND_gate one(c,a,b);
assign i=c;
not(o,i);
specify
specparam
Tpd_0_1 = 2:2:2,
Tpd_1_0 = 2:2:2;
(i=>o)=(Tpd_0_1,Tpd_1_0);
endspecify
endmodule

module system_clock(clk);
parameter period=100;
output clk;
reg clk;
initial clk=0;
always
begin
#(period/2) clk=~clk;
#(period-period/2)clk=~clk;
end
always@(posedge clk)
if($time>1000)#(period-1)$stop;
endmodule