輸入10秒delay的NAND

module top;
reg a,b;
wire i,o;
initial
begin
#10 a=0; b=1;
#10 a=1;
#10 b=0;
#10 b=1;
#10 a=0;
end
initial
#100 $finish;
AND_NOT two(o,i,a,b);
endmodule

module AND_gate(c,a,b);
input a,b;
output c;
and(c,a,b);
specify
specparam
Tpd_0_1 = 3:3:3,
Tpd_1_0 = 3:3:3;
(a=>c)=(Tpd_0_1,Tpd_1_0);
(b=>c)=(Tpd_0_1,Tpd_1_0);
endspecify
endmodule

module AND_NOT(o,i,a,b);
input a,b,i;
output o;
wire c;
AND_gate one(c,a,b);
assign i=c;
not(o,i);
specify
specparam
Tpd_0_1 = 2:2:2,
Tpd_1_0 = 2:2:2;
(i=>o)=(Tpd_0_1,Tpd_1_0);
endspecify
endmodule