真值表~
a0 a1 b0 b1 f
0 0 0 0 0
0 0 0 1 1
0 0 1 0 1
0 0 1 1 0
0 1 0 0 1
0 1 0 1 1
0 1 1 0 0
0 1 1 1 0
1 0 0 0 1
1 0 0 1 0
1 0 1 0 1
1 0 1 1 1
1 1 0 0 0
1 1 0 1 0
1 1 1 0 1
1 1 1 1 1
程式碼~
module top;
system_clock #200 clock1(a0);
system_clock #100 clock2(a1);
system_clock #50 clock3(b0);
system_clock #25 clock4(b1);
many abc(f,a0,a1,b0,b1);
endmodule
module many(f,a0,a1,b0,b1);
input a0,a1,b0,b1;
output f;
wire a0_1,a1_1,b0_1,b1_1,c,d,e,g,h;
not(a0_1,a0);
not(a1_1,a1);
not(b0_1,b0);
not(b1_1,b1);
and(c,a0_1,a1,b0_1);
and(d,a0,a1_1,b1_1);
and(e,a1_1,b0,b1_1);
and(g,a0_1,b0_1,b1);
and(h,a0,b0);
or(f,c,d,e,g,h);
endmodule
module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)if($time>1000)#(PERIOD-1)$stop;
endmodule
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